1. Technical Field
The present invention pertains to a processing system or processor including a computing architecture capable of performing a limited number of individual threads (i.e., instruction streams) on an unlimited number of data streams. This architecture is preferably suited for systems where a great deal of symmetry exists between the data streams and the algorithms processing them, but in which each data stream is a distinct entity.
The design of a Multiple Thread Multiple Data (MTMD) processor according to the present invention includes both a hardware architecture and a software technique, both of which are described below. In addition, the software design methodology needed to efficiently use the MTMD processor is also described below.
2. Discussion of Related Art
There are many data processing applications wherein multiple streams of data may be processed with the same sequence of instructions. In view of these applications, the development of the Single Instruction Multiple Data (SIMD) architecture has progressed to the Multiple SIMD (MSIMD) and Multiple Instruction Multiple Data (MIMD) architectures. The applications for these architectures typically include weather and other system simulations, video and image processing. The goal of these architectures is to solve a single problem that involves large and sometimes multiple vector operations. As such, the current state of the SIMD architecture is based on one or more instruction streams that control and centrally allocate a pool of data processors. These data processors individually perform a relatively small portion of the overall application and are interconnected through a matrix or common data memory structure.
The MTMD processor of the present invention incorporates multiple unique circuits into the basic MSIMD architecture to create a machine that is better suited for performing many individual small tasks having some instruction commonality. These individual tasks each have an individual execution life and may transition through various phases of the total algorithm during that execution life. For example, there may be 1000 data streams with seven algorithm phases, thereby enabling application of a large amount of commonality. Since the phase transitions of a data stream are based solely on that data stream, the individual data processing elements cannot be under the control of the instruction stream or a central control unit, but rather, must have control over themselves.
This new improved architecture is referred to herein as the Multiple Thread Multiple Data (MTMD) architecture whereby the term "thread" physically refers to an instruction stream or, with respect to the MTMD architecture, a repeated circular software thread (e.g., a repeating set of instructions). Each data stream has the ability to select a thread that repeatedly processes the data stream (e.g., the thread instructions are executed repeatedly) whereby the data stream selectively executes instructions of the selected thread.
Data and voice communications networks utilize many applications that are suited to the MTMD architecture. Some examples of such applications include:
Echo cancellation in the Public Switched Telephone Network (PSTN) PA1 Global System for Mobile Communication or Groupe Special Mobile (GSM) speech compression in the cellular telephone network PA1 Primary Rate Integrated Services Digital Network (ISDN) V.120 negotiations and compression PA1 Analog Modem V.8, V.34 and others PA1 Central cite encryption PA1 Ethernet packet switching
Applying the MTMD architecture to a public network incurs a new set of restrictions on size and power of the implementing circuit, thereby enabling incorporation of additional features to reduce power consumption. Typically, the SIMD architecture is utilized in supercomputers, high end video workstations and medical imaging where size, power and cost may not be primary concerns.